1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device having a multilayer wiring structure, with an improved version of the step of forming an interlayer insulation layer.
2. Description of the Related Art
In accordance with an increase in the density of integration of a semiconductor device, a so-called multilayer interconnection, in which wiring materials are formed on a substrate in a multilayered manner, is developed. Consequently, the method of manufacturing a semiconductor device having such a multilayer interconnection structure, is becoming complex and the number of steps involved are being increased.
Especially, the steps of forming wiring layers greatly influences the manufacturing cost of the semiconductor device. Therefore, in order to decrease the cost required to manufacture a semiconductor device, it is very important to facilitate the manufacture steps, and decrease the number of manufacturing steps for forming wiring layers.
The following is a description of a conventional process for forming a multilayer interconnection structure.
To begin with, the first wiring material used for an underlying wiring layer is deposited on a substrate, and the underlying wiring layer is subjected to patterning. The first insulation film is formed on the patterned underlying wiring layers, as well as to fill the spaces between the adjacent underlying wiring layers.
At this point, due to the patterning of the underlying wiring layers, steps are created on the surface of the first insulation film. These steps may adversely affect the deposition of a second wiring material serving as an overlying wiring layer, and the patterning of the overlying wiring layer, which may results in serious defects such as breakage of wiring in the overlying wiring layer and occurrence of a short circuit.
As a solution to such drawbacks, conventionally, the surface of the first insulation film, which is the underlying layer of the second wiring material, is planarized by resist etchback in order to planarize the steps before the second wiring layer is deposited on the first insulation film.
The conventional process of forming an interlayer insulation layer, in which the second insulation film is laminated on the first insulation film, proceeds in the following manner. That is, after a first insulation film is formed in the first layer forming step, the first insulation film is planarized in the planarizing step, and then the second insulation film is formed in the second film forming step. The conventional interlayer insulation film forming process, which proceeds in the above-described manner, does not meet with the aforementioned demand, i.e. a decrease in the number of manufacturing steps a multilayer interconnection structure.
In the meantime, as an example of the technique of planarizing the surface of an interlayer insulation film, which can satisfy the demand of decreasing the number of manufacturing steps for making a multilayered interconnection structure, an APL (Advanced Planarization Layer) process is disclosed in documents, namely, Matsuura et al., IEEE Tech. Dig., pp 117, 1994 and Semiconductor International (December 1994).
In this APL process, during the formation of an interlayer insulation film, a SiH.sub.4 gas and H.sub.2 O.sub.2 (hydrogen peroxide solution) which serves as an oxidizer are made to react with each other at a low temperature (for example, about 0.degree. C.) in a vacuum atmosphere, thus forming a reflow SiO.sub.2 film on an underlying wiring layer. The reflow SiO.sub.2 film is defined as a film having a reflow form of which the surface tomography is smoothed over lower wires.
The reaction which takes place in the process is expressed in a chemical formula in Formula 1 below. In this reaction, the reflow is promoted by having an Si--H group.
Formula 1 EQU SiH.sub.4 +H.sub.2 O.sub.2 .fwdarw.Si(OH).sub.4 .fwdarw.SO.sub.2 +2H.sub.2 O.uparw.
In the above-described step, the filing the spaces between underlying wiring portions with an insulation film and the planarization of the surface of the insulation film can be carried out at the same time, and the manufacturing steps which take, up to the planarization can be completed by one film forming step. Consequently, the number of manufacturing for steps forming a multilayered interconnection structure can be decreased.
In this film formation process, before the reflow SiO.sub.2 film is formed, the first interlayer insulation film (the first plasma CVD insulation film) is formed on the underlying wiring layer by an ordinary plasma CVD method. After the formation of the reflow SiO.sub.2 film, the second plasma CVD insulation film serving as the second interlayer insulation film (cap layer) is formed thereon by the ordinary plasma CVD method. Then, furnace annealing is carried out.
However, the relative dielectric constant of an ordinary SiO.sub.2 film formed by heat oxidation is only about 3.9, whereas that of the reflow insulation film formed by the process described in the above documents is as high as about 4.5 to 4.7. Thus, the demand of a low relative dielectric constant:, which is required by a high-speed device, cannot be easily satisfied.
Further, as another conventional example, NIKKEI MICRODEVICES, pp 105, July 1995, particularly, TABLE 1 provided on page 109, discloses a method in which an aromatic compound such as polyimide, which serves as a low dielectric material, is formed on a semiconductor substrate by spin-coat, so as to manufacture an insulation film having a relative dielectric constant lower than that of an ordinary SiO.sub.2 film.
In this method, a low dielectric constant is achieved by involving a cyclic or network structure as shown in Formula 2 below; however such a method does not work for a good reflow property, in which the surface of the insulation film which covers a fine pattern as of an underlying wiring layer is planarized. ##STR1##